Carry Look-Ahead Adder
From the Ripple Carry Adder, we saw that
Note that:
and are generated after 1 gate delay - Each
can be implemented using a 2-level SOP using , , and . Hence all can be computed with 2 more gate delays. - Since
, one more gate delay is incurred to produce all
Unfortunately, for a large number of bits, carry look-ahead adders become too expensive, but they are faster than ripple adders.
Circuit
Hierarchical Carry Look-Ahead Adder
A hierarchical carry look-ahead adder uses a number of smaller carry look-ahead adders in a cascaded fashion to build a larger adder. It's much more practical, combining the Ripple Carry Adder with the carry look-ahead adder.
Circuit