Instructions

ADD R2, R0, #1

where #1 is an immediate value (i.e constant)

reg[2] <- reg[0] + 1

Format: <op>{cond}{S} Rd, Rn, Op2

• op: operation mnemonic
• cond?: ARM V7 Assembly#Conditions
• S?: should set flags in PSR
• Rd: dest. register
• Rn: Operand 1 (reg.)
• Op2: Operand 2 (reg. or immediate data)

If we try -1 + -1:

with a carry bit , the PSR flags will be set to:

• C: true
• Z: false
• V: false
• N: true

ADDS R2, R0, #1

the S flag is used to "set" PSR flags

reg[2] <- reg[0] + 1, PSR <- N, Z, V, C

ADDEQ R5, R3, R4

if (Z == 1) reg[5] <- reg[3] + reg[4]

There is no NOT operator. Instead, use EOR against -1.

Program in C:

i--;
if (i < 0) {
    i += 10;
}

Equivalent in ARM ASM:

SUB R1, R1, #1
ADDLT R1, R1, #10

where i is R1.

Equivalent shorthand:

SUB R1, #1
ADDLT R1, #10

Flexible operands can either be:

• A constant (an 8-bit value) shifted 0-31 bits, which is immediate data encoded in the machine instruction
  • e.g ADD R2, R0, #1
• A register value shifted 0-31 bits

Format: <op>{S}{cond} Rd, Rn, <Rs | #n>

• Rs | #n # of bit positions to shift

ADD R2, R0, R1, LSL #2

Same as

reg[2] <- reg[0] + (reg[1] << 2)

Move 0x1234ABCD into R2

MOV R2, #0xABCD ; now R2 is `0000ABCD`
MOVT R2, #0x1234 ; now R2 is `1234ABCD

Format: <op>{size}{cond} Rd, <address>

• op: operation mnemonic
• size?: size to load/store, defaults to word (4 bytes)
  • B byte
  • H half word (2B)
  • SB signed byte
  • SH signed halfword
• cond?: [[ARM V7 Assembly#Conditions]]
• Rd: dest. register
• address: see below

Treats register value like a pointer

1. With immediate offset
   • <address> = [Rn {, #offset}]
2. With register offset
   • <address> = [Rn, ± Rm {, shift}]

LDR R1, [R0]

reg[1] <- mem[reg[0]]
R1: [1234 ABCD]

LDR R2, [R0, #4]

reg[2] <- mem[reg[0] + 4]
R2: [AAAA 5555]

LDRSB R3, [R0]

Load signed byte

R3: [FFFF FFCD]

LDR R1, [R0, -R2]

reg[1] <- mem[reg[0] - reg[2]]

LDR R1, [R0, R2, LSL #2]

reg[1] <- mem[reg[0] + (reg[2] << 2)]

Indexed addressing allows us to auto-increment the value of a register by some offset before or after using it. Think of it like ++i vs i++.

• Normal: <address> = [Rn, #offset]
• Pre-indexed: <address> = [Rn, #offset]!
• Post-indexed: <address> = [Rn], #offset

LDR R3, [R1, #4]!

reg[3] <- mem[reg[1] + 4]; reg[1] <- reg[1] + 4

LDR R3, [R1], #4

reg[3] <- mem[reg[1]]; reg[1] <- reg[1] + 4

Format: LDR{size}{cond} Rd, label

• label: name for a line of code

LDR R1, SUM

reg[1] <- mem[&SUM]

where SUM is some label to some line in the code

Format: ADR{cond} Rd, label

• label: label of some line of code

ADR, R2, SUM

reg[2] <- &SUM

Format: <op>{cond}{address-mode} Rn{!}, reg-list{^}

• op: operation mnemonic
• cond?: [[ARM V7 Assembly#Conditions]]
• address-mode: [[The Stack#Full vs Empty, Ascending vs Descending Stack]]
  • FD full descending
  • FA full ascending
  • ED empty descending
  • EA empty ascending
• Rn base register for the load operation (e.g stack pointer for loading)
• ! specifies base register write back (i.e base register gets updated after the transfer, by one word for each register in the register list)
• reg-list comma separated list of register names and ranges enclosed in braces

STMFD r13!, {r0-r5, LR} ; Push r0-r5 and link register onto stack
LDMFD r13!, {r0-r5, PC} ; Pop r0-r5 and the link register into the program counter from stack

Format: B{cond} label

• label: label of some line of code

Compares two operands and updates the PSR flags (N, Z, C, V). Operands remain unchanged.

Format: <op>{cond} Rn, Op2

Format: <op> Rn, label

if (x == 0) {
    y++
} else {
    y--;
}

With CMP:

CMP R0, #0
ADDEQ R1, #1
SUBNE R1, #1

With CBZ/CBNZ:

     CBZ R0, ELSE
     ADD R1, #2
ELSE SUB R1, #1