Control
Also see: Datapath#Datapath with Control
Recall the different datapath stages:
- Stage 1 (instruction fetch): has the same behaviour for all instructions
- Stages 2-5 (instruction decode, execute, memory, writeback): the behaviour depends on the instruction
- Control logic generates control signals based on the opcode
Definition
Control is Combinational Logic telling the datapath how to behave
Table
Control signal values
| Instruction | Reg2Loc | ALUSrc | MemToReg | Reg Write | Mem Read | Mem Write | Branch | ALUOp |
|---|---|---|---|---|---|---|---|---|
| ADD | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 10 |
| LDR | x | 1 | 1 | 1 | 1 | 0 | 0 | 00 |
| STR | 1 | 1 | x | 0 | 0 | 1 | 0 | 00 |
| CBZ | 1 | 0 | x | 0 | 0 | 0 | 1 | 01 |
where the x's represent don't cares
Reg2Loc,ALUSrc, andMemToRegare selected by a multiplexer- The branch signal:
if (branch == 1 && zero == 1) PC <- branch target else PC <- PC + 4
| ALUOp value | Meaning |
|---|---|
| 00 | add |
| 01 | pass input b |
| 10 | check opcode (of R-type instruction) |
Table
Determining control signal function:
| Instr | Opcode | Control Signal | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
I31 |
I30 |
I29 |
I28 |
I27 |
I26 |
I25 |
I24 |
I23 |
I22 |
I21 |
Reg2Loc |
ALUSrc |
|
ADD |
1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 |
LDR |
1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | x | 1 |
STR |
1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
CBZ |
1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | x | x | x | 1 | 0 |
If these were the only instructions, then:
- Reg2Loc = I29
- ALUSr = I30