Datapath

(see Sequential Circuits)

• Instruction is fetched from instruction memory
• The instruction address is incremented (PC += 4) and latched into the PC register at the end of clock cycle

(see multiplexer)

• Decodes instruction fields (opcode, reg#, offset, etc)
• Read registers:
  • Read reg #1 = Rn (ADD, LDR, STR)
  • Read reg #2 =

(see sign extend)

• The ALU performs arithmetic operations
  • Addition for ADD
  • Calculates memory address for LDR/STR
  • Sets zero status for CBZ
• ALU zero = Rt == 0
• The branch adder calculates the branch target address (PC + (offsett << 2))

For loads (LDR): assert read, output is on read data
For stores (STR): assert write, input is from Rt (from #Stage 2 Instruction Decode (ID))

• A result is written back to a register
• Write reg #
• Write data