Design Paradigms for ISAs
See Architecture#Instruction Set Architecture (ISA)
Complex Instruction-Set Computer (CISC)
Properties
- Common until early 1980s
- Very hard to pipeline
- Instruction set has features to make assembly programming easier, such as:
- Complex operations
- E.g
movsb
(in x86): you can copy a byte string in memory
- E.g
- Operands for ALU instructions can come from memory
- E.g
add d0, label
(in M68000)mem[label] <- [d0] + mem[label]
- E.g
- Complex addressing modes
- E.g
ldr r1, [r0, #4]!
(in arm)
- E.g
- Complex operations
- Smaller executables
- Variable instruction length
- E.g
x86
instructions are 1-15 bytes in size
- E.g
Reduced Instruction-Set Computer (RISC)
Properties
- Introduced in 1980s
- Facilitates pipelining (speeds up execution)
- Have load-store architectures
- ALU operands come from registers (on immediate values)
- Only load or store instructions access memory
- Executables are about 30% larger than a CISC ISA
- Fixed instruction size
Example
Convert add, d0, label
(M68000 = CISC) into ARM
solution
LDR R1, =label
LDR R2, [R1]
ADD R2, R0, R2
STR R2, [R1]
Example processor: LEGv8
-
Simplified version of ARMv8
-
Instructions: all 32 bits (4 bytes)
-
Registers: 64-bit, x0-x31
-
Representative instructions:
ADD, LDR, STR, CBZ
-
ADD Rd, Rn, Rm
- R-format (register format)
- E.g
ADD X2, X1, X0
10001011000 00000 000000 00001 00010
-
LDR X1, [X0, #8]
- D-Format (data format)
- E.g
LDR X1, [X0, #8]
- `11111000010 000001000 00 00000 00001``
-
STR
- also d-format -
CBZ X0, label
(CBZ X0, [PC, #16]
)- CB-format
- Signed offset is multiplied by 4 before being added to the PC, so we get even more space, AND we can go backwards
- E.g
CBZ X0, label
(label is[PC, #16]
)10110100 0000000000000000100 00000