Bus Transfers

See clock

1. The bus master (processor) outputs an address and asserts read () at the start of cycle
2. The bus slave (memory or peripheral) outputs data in the second half of the clock cycle
3. The bus master latches (stores) the data at the end of cycle

1. Master outputs the address, asserts write () and outputs data at the start of cycle
2. Slave latches the data in the second half of the cycle