Caches
todo diagram
E.g cache starts empty
`LDR` at `0x48`: - Not found (cache miss) - Fetch all of B1 from memory into cache line 0 - Cache delivers the data (15) to the processorLDS at 0x50
- data is found (cache hit)
- cache delivers the data (20) to the processor
Operating Principles
- Caches work on the principal of locality of reference (memory reference)
- The idea is that if a processor needs data or an instruction from memory:
- it will need the same data/instruction again soon (temporal locality)
- It will need other nearby data/instr. (spacial locality)
Operation:
- Stores data/instr. that have been recently used
- Retrieves data/instr. from memory in multi-word blocks
Mapping Schemes
- Determines where the cache stores a block from memory
- Fully associative (huh?)
If we have a block
| Num | Tag | Valid? | data |
|---|---|---|---|
| 0 | B1 | 10 15 20 ... 45 |
|
| 1 | 0 | ||
| 2 | 0 | ||
| 3 | 0 |
- Most flexible => highest hit rates
- Most expensive: it must search all tags in parallel using
(number of lines) comparators
MISSING STUFF
e.g dual core
Cache Performance
Average memory access time:
E.g
Assume just L1 (no L2 or L3)
I zoned out here.
Now assume L2:
Parameters:
L2
L1
For an L3: