DDR Standard
- All bus transfers are 64 bits (per channel)
- A "rank" of memory chips provides the data
- The chips are mounted on a DIMM (dual inline memory module)
todo diagram:
dashed: sometimes there's a chip there sometime's there's not
Generation | Release date | Bus clock | Bus transfers | Bandwidth |
---|---|---|---|---|
DDR1 | 1998 | |||
... | ||||
DDR5 | 2020 |
Naming convention:
E.g
PC - 12500
- DDR3
- Bus transfer rate:
- Bus clock rate: