DRAM Chips

[!example]
16 words x 4-bit word chip (64 bits total)

Logical view

todo missing stuff

• Matrix dimensions:
  • Total bits = (16 Mi)
  • (4096)
  • We want a matrix of bit cells
  • Each row holds
• The memory controller divides the address into row and column numbers
  • E.g
• Since pins are expensive, the row # and col # share the same pins

Logical view:

External view:

DRAM timing

Asynchronous DRAM

• The memory controller gives the row number (and asserts ), waits, then gives the column number (and asserts ), waits, then the data is transferred

Handout: memTiming

Funny shape: multi-bit value

Fast Page Mode (FPM DRAM)

FPM: fast page mode, funny thing from the 90s that allows for faster read "ancient history for you, I was done my masters by then"

Memory controller gives the row number once, and then specifies various column numbers.

Synchronous RAM (SDRAM)

• Commands and data transfers are synchronized to the bus clock
• A row is buffered and data is transferred in bursts of 2, 4, 8, 16, ... words (see memTiming)

Double Date Rate SDRAM (DDR)

• Data is transferred on rising and falling edges of the bus clock (see memTiming)

DRAM Performance

• Latency: time from start of request to start of data transfer (e.g 5 cycles in memTiming diagrams)
• Bandwidth: throughput or volume of data per unit time (MB/s)

E.g assume: data size , bus clock , words read = 2