Analysis of ASCs

1. Write logic expressions for the next-state () and the output () in terms of the current state () and the input ()
2. Construct the excitation table
3. Obtain the flow table
4. Draw the state diagram if desired.

A gated D latch circuit with a hypothetical delay element:

We can write:

(see consensus law)

Below is the excitation table, with the stable states circled.

A state is stable when its next state is the same as its current state.

We can construct a flow table:

State diagram:

Analysis of a DFF circuit made with D-latches with delay elements inside the latches (Asynchronous Sequential Circuits#Modelling Gate Delay).

We can write

by definition.

This gives us the state assigned table:

changing this to a flow table:

We can also remove the following redundant elements:

The reason being that when at S2, it is stable. In fundamental mode, only one input may change at a time (i.e C and D cannot change at the same time), so it won't reach at S2.

The same reasoning applies to at S3.

We arrive at the state diagram: