Asynchronous Sequential Circuits
- Analysis of ASCs
- Asynchronous Sequential Circuits
- Hazard Free Circuits
- Race-Free State Assignment
- State Reduction of ASCs
- Synthesis of ASCs
Unlike a SCS, and ASC does not involve a clock and therefore no Flip-Flops. However, these are still finite-state machines, and they consist of combinational logic with feedback paths. The feedback creates a memory effect (e.g SR latch).
where:
- W: circuit input
- Q: feedback or current state
- Z: circuit output
Moore Machine
See Moore machine
Mealy Machine
See Mealy machine
Example Circuits
The RS-NOR latch is an example of an asynchronous sequential circuit if we make some changes:
The gated D latch rearranged:
Stable State
A circuit is in stable state when all internal signals stop changing
Fundamental Mode
A circuit is in fundamental mode if the following restrictions hold:
- Only one input is allowed to change at a time
- The input changes only after the circuit is stable
We assume fundamental mode for our circuits unless stated otherwise.
Modelling Gate Delay
For ASC, we assume gates offer no propagation delay. However, this will be compensated by a hypothetical delay element on the feedback path, allowing us to separate current and next states.
SR latch with delay element
Gated D latch with delay element