Flip-Flops

Abstract

D Flip-Flop
- Positive edge triggered: on clock rising edge,
- Negative edge triggered: on clock falling edge,
T Flip-Flop
- On clock rising edge, if , then gets inverted
JK Flip-Flop
- Acts as a T flip-flop when , and a D flip-flop when

Edge Triggered Flip-flops

A flip-flop has an enable input (e.g clock) and can be viewed to have two gated latches
The state of a flip-flop responds to input data signals only at one of the edges (usually rising) of the control signal
Since clock edges are almost instant, a flip-flop can only change state once per cycle

D Flip-Flop (DFF)

Circuit

When clock = 1, follows the changes of , and will not change
When clock = 0, stops following the changes of , and becomes

Therefore, L2 only has one change per cycle. From the perspective of an outside observer, the state will change on the falling edge of the clock. This is also known as a D-flip-flop, or DFF.

Timing Diagram

Notice how "copies" the state of on the falling edges. We can make this a positive-edged flip-flop by putting the NOT gate in front of the L1 clock instead.

Symbols

Timing Diagrams

Notice:

of the gated latch copies the value of only when clock is high
of the positive edge DFF copies the value of only on the rising edge of the clock
of the negative edge DFF copies the value of only on the falling edge of the clock

Characteristic Table

D
0	0
1	1

Excitation table

D
0	0	0
1	0	1
0	1	0
1	1	1

DFF With Clear and Preset

The state of the DFF can be cleared to 0 or preset to 1
Clear and preset are asynchronous operations, which can be made synchronous by putting it with an AND gate with before D

Symbol

If preset = 0, then Q = 1
If clear = 0, then Q = 0
Preset and clear should not be activated at the same time

Timing Analysis with Flip-Flops

It takes time for gates to change their output values according to the inputs
I.e there are propagation delays due to resistance, capacitance, etc

Changes in flip-flop outputs occur at the active clock edge
Three timing parameters that are especially important:
- Setup time ()
- Hold time ()
- Clock-to-output time ()
If we fail to meet any of these time parameters, we have a timing violation and the circuit will behave unexpectedly

Setup Time

Definition

The amount of time that the data inputs need to be held stable prior to the arrival of the active clock edge

Hold Time

Definition

The amount of time that the data inputs need to be held stable after the arrival of the active clock edge

Clock-to-output Time

Definition

The amount of time it takes for the output to become stable (at its new value) after the arrival of the active clock edge

T Flip-Flop (TFF)

Implementation

(see XOR gate)

Characteristic Table

T
0
1

Excitation Table

T
0	0	0
1	0	1
0	1	1
1	1	0

Symbol

Timing Diagram

Notice how when , gets inverted, but stays the same when

J-K Flip-Flop (JKFF)

Implementation

Characteristic Table

J	K
0	0
0	1	0
1	0	1
1	1

Excitation Table

J	K
0	x	0	0
1	x	0	1
x	0	1	1
x	1	1	0

where x is a don't care.

Full form:

J	K
0	0	0	0
0	0	1	0
0	1	0	0
0	1	1	0
1	0	0	1
1	0	1	1
1	1	0	1
1	1	1	0

Tldr

The circuit acts as a T flip-flop when , and a D flip-flop when

Symbol