Latches
Basic Latch
Responds with changes in the signal level of input data
SR-NOR Latch
Latch made from NOR gates
Circuit
Truth Table
| S | R | ||
|---|---|---|---|
| 0 | 0 | nc | nc |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
Where nc denotes no change.
- When
, is reset to 0 - When
, is set to 1
Intuition
Timing Diagram
SR-NAND Latch
Latch made from NAND gates
Circuit
Truth Table
| S | R | ||
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | nc | nc |
Gated Latch
A basic latch with an enable input as well (e.g clock).
Circuit
Truth Table
| clk | S | R | Q | Q' |
|---|---|---|---|---|
| 0 | x | x | nc | nc |
| 1 | 0 | 0 | nc | nc |
| 1 | 0 | 1 | 0 | 1 |
| 0 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | x | x |
Gated D Latch
Circuit
Truth Table
| clk | D | Q(t + 1) |
|---|---|---|
| 0 | x | Q(t) / nc |
| 1 | 1 | 1 |
| 1 | 0 | 0 |
Timing Diagram
Symbol