Synthesis of SSCs

1. Devise a state diagram
2. Derive a state table and reduce states if possible
3. Perform state assignment to get an state assigned table
4. Obtain the next-state and output expressions

Circuit Specification

• The circuit has one input and one output
• All changes in the circuit occur at the positive edge of a clock signal
• The output is equal to 1 if during two immediately preceding clock cycles, the input was equal to 1.
  Otherwise, the output is equal to 0.

State Diagram

• Node A represents the starting state and it is also the state of the circuit will reach after an input is applied
• Node B represents the state after the first
• Node C represents the state after all subsequent

State Table

State Assigned Table

• Let , , and be represented as , , and respectively (arbitrarily)
• Let and be the next-state variables

Where is a "don't care". Notice how this table is almost identical to the one above.

Using K-maps (or by inspection), we can write , , and .

Circuit Block Diagram

DFF Based Circuit Diagram

Improved State Assignment

This time, let be represented as

Again with K-maps (or by inspection), we can write , , and

Circuit Diagram from Improved State Assignment

One-Hot State Assignment

Logic expressions:

Circuit Specification

• The circuit has one input and one output
• The output is equal to 1 if during immediately preceding clock cycle, and current clock cycle, the input was equal to 1.
  Otherwise, the output is equal to 0.

State Diagram

Unlike the Moore machine, since the output depends on the current state and present input, the outputs must be shown on the arcs, not the nodes.

State Table

State Assigned Table

Circuit Diagram